The semiconductor industry faces a challenge as chip-to-chip interconnect scaling lags behind on-chip scaling, creating a bottleneck in system performance. Advanced packaging’s role in improving system performance is hindered by limitations such as beachfront I/O density, die integration issues, and difficulties in achieving high-bandwidth chip-to-chip interconnects, mainly due to variations in chip thickness and die placement accuracy. Patterning system constraints compound these challenges, affecting multi-die integration. The slow cycle times of mask-based lithography technologies contribute to development delays in the Heterogeneous Integration Roadmap (HIR).

Multibeam addresses these issues with its Multi-Column E-beam lithography (MEBL) solution. This maskless technology enhances multi-die integration with a large write field, high DoF, ultra-fine resolution, and adaptable writing, supporting diverse components on a single substrate for AI applications. MEBL makes it possible to pattern more than 10X larger than current interposers, facilitating wafer-scale integration for processors like HPC, GPUs, and AI engines. With more than 100X DoF improvement over optical lithography, it enables advanced 3D structures and high-resolution interconnects, resulting in a 10x-100x increase in chip-to-chip interconnect bandwidth. This technology expedites in-package data analysis, inference, and decision-making with low power and low latency, promising breakthroughs in chips-first and chips-last packaging and on-wafer extended integration.

Multibeam’s technology accelerates time-to-market for multi-die packages and overcomes throughput limitations. Its scalable modular architecture allows for seamless transitions from pilot to production. Its adaptable and extendable patterning capabilities and the ability to customize substrates and implement design changes without masks position this technology to drive advancements in silicon integration for future generations.